1. Field of the Invention
The present invention relates to a method for performing a logic built-in-self-test on electronic circuits, especially on integrated circuits. Further the present invention relates to an electronic circuit with a plurality of storage elements and logic circuits and at least a logic built-in-self-test engine.
2. Description of the Related Art
Integrated semiconductor circuits comprise a plurality of storage elements and logic circuits. The storage elements may be realized as flip-flop elements, for example. The logic circuits may be realized as gate logic circuits. During the manufacturing the integrated circuits have to be tested in order to detect defects on the integrated circuit. An example of such a method is a logic built-in-self-test (LBIST). The logic built-in-self-test allows the test of the chip logic at the clock speed of the system.
The LBIST uses pseudo-random pattern generators (PRPG) to initialize LBIST-able scan chains, referred to as LBIST stumps. The LBIST stump is formed by a plurality of scan-able storage elements. Like other storage elements the scan-able storage element comprises a data input and a data output. Additionally the scan-able storage element comprises a scan input and a scan output. The scan output of one scan-able storage element is connected to the scan input of the next scan-able storage element. In this way the scan-able storage elements form the LBIST stump.
The PRPG generates pseudo-random patterns. Said pseudo-random patterns are driven into the LBIST stumps. The PRPG initializes the LBIST stumps through their scan inputs at the maximum scan frequency. Subsequently, the LBIST switches to the system clock frequency of the product and exercises the functional logic between the LBIST stumps and updates the storage elements of the LBIST stumps. After the functional logic updates, the LBIST stumps scan out the updated values into multiple-input-signature registers (MISR), while simultaneously scanning in new values from the PRPG. The results from the LBIST stump are serially compressed into the MISR. The registers of the MISR capture a signature that is used to identify faults after running enough LBIST iterations.
The non-deterministic nature of the PRPG data causes a problem for those parts of the logic circuit, which require special constraints on the data values. For example, a pass-gate multiplexer needs a one-hot or all zero input value in its control register in order to avoid short circuits within the multiplexer. Other circuits are prone to voltage drops, when operating with illegal data values like on-chip memories that have more than a single word-line asserted at a time.
FIG. 6 illustrates a schematic diagram of a conventional LBIST structure. A number of LBIST stumps 10 are arranged between the PRPG 26 and the MISR 28 according to the prior art. Between the LBIST stumps 10 random logic blocks 22 are arranged. Each LBIST stump 10 comprises a plurality of storage elements 14 for unconstrained values as shown in FIG. 7.
FIG. 7 illustrates a schematic diagram of a part of an integrated circuit with the LBIST engine according to the prior art. The integrated circuit includes a first LBIST stump 10 and a second LBIST stump 12. The first LBIST stump 10 comprises a plurality of storage elements 14 for unconstrained values. The second LBIST stump 12 comprises a first portion 30 and a second portion 32. The first portion 30 of the second LBIST stump 12 includes a plurality of storage elements 14 for unconstrained values. The second portion 32 of the second LBIST stump 12 includes a plurality of storage elements 16 for constrained values. The integrated circuit includes further a constrained logic block 18 and three random logic blocks 20, 22 and 24. The constrained logic block 18 requires the constrained input values. The constrained logic block 18 could be the pass-gate multiplexer above, for example, which requires the constrained input values.
The paper “Testing digital circuits with constraints” by Ahmad A. Al-Yamani, Subhasish Mitra and Edward J. McCluskey (Proceeding of the 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 195-203, 2002) focuses on detecting and resolving illegal states for one-hot constraints by using a logic that is directly added to the circuit under test. However, this method works only for one-hot constraints, but not for arbitrary constraints. Furthermore, this method requires a change of the circuit under test by adding additional resolution logic. Said additional logic increases the complexity of the circuit under test and its critical paths.
The paper “Built-in constraint resolution” by Grady Giles, Joel Irby, Daniela Toneva and Kun-Han Tsai (International Test Conference 2005, IEEE) relates to the maintaining of the correct state for one-hot multiplexer structures and buses. Additional special scan storage elements and an additional decode logic are added to the circuit under test. This method requires an application specific change in the circuit under test. Further, this method requires a high logic complexity.